The present invention relates to a recording head substrate, a recording head using the recording head substrate, and a recording apparatus using the recording head.
A recording head mounted on a conventional ink-jet recording apparatus has a circuit arrangement, as shown in FIG. 10. In such printing head, electro-thermal conversion elements (heaters) and a driving circuit therefor are formed on a single substrate using the semiconductor process technique, as disclosed in, e.g., Japanese Patent Laid-Open No. 5-185594.
Referring to FIG. 10, reference numeral 401 denotes electro-thermal conversion elements (heaters) for generating heat energy; 451, power transistors each for supplying a desired current to the corresponding heater 401; 502, a shift register for temporarily storing image data indicating whether or not currents are supplied to the individual heaters 401 to eject ink from the nozzles of the recording head; 503, an image data input terminal for serially inputting image data (DATA) for turning on/off the heaters 401; 504, an input terminal provided to the shift register 502 to receive transfer clock pulses (CLK); 501, latch circuits for storing image data (DATA) corresponding to the heaters 401 in units of heaters; 505, a latch signal input terminal for inputting a latch timing signal (LT) to the latch circuits 501; 506, switches for determining the supply timings of currents to the heaters 401; 452, a power supply line for applying a predetermined voltage to the heaters to supply currents; and 453, a GND line into which currents that flowed through the heater 401 and the power transistor 451 flow.
Note that the number of bits of image data stored in the shift register 502, the number of power transistors 451, and the number of heaters 401 are equal to each other.
FIG. 11 is a timing chart of various signals for driving the recording head driving circuit shown in FIG. 10.
The operation of the recording head driving circuit shown in FIG. 10 will be described below with reference to FIG. 11. A number of transfer clock pulses (CLK) corresponding to the number of bits of image data stored in the shift register 502 is input to the transfer clock input terminal 504. In this case, assume that data is transferred to the shift register 502 in synchronism with the leading edge of the transfer clock pulses (CLK), and image data (DATA) for turning on/off the heaters 401 is input from the image data input terminal 503.
Since the number of bits of image data stored in the shift register 502, the number of heaters 401, and the number of power transistors 451 for current driving are equal to each other, transfer clock pulses (CLK) corresponding to the number of heaters 401 are input to transfer the image data (DATA) to the shift register 502. Thereafter, a latch signal (LT) is supplied to the latch signal input terminal 505 to latch image data corresponding to the heaters 401 in the latch circuits 501.
Thereafter, when the switches 506 are set in the "ON" state for an appropriate period of time, currents are supplied to the power transistors 451 and heaters 401 via the power supply line 451 in correspondence with the ON durations of the switches 506, and the currents then flow into the GND line 453. At this time, each heater 401 generates heat required for ejecting ink, and ink corresponding to the image data (DATA) is ejected from the nozzles of the recording head.
The above-mentioned arrangement is conventionally known. Furthermore, a recording head having an arrangement shown in FIG. 12, as an improved arrangement of FIG. 10, is also proposed.
Referring to FIG. 12, reference numeral 410 denotes nMOS field effect transistors (FETs) serving as power transistors for supplying desired currents to the heaters.
When this circuit arrangement is compared with that shown in FIG. 10, the arrangement shown in FIG. 10 uses Darlington-connected npn transistors as each power transistor. In this arrangement, a logic circuit such as a shift register, a latch, or the like normally uses a CMOS gate, and a BiCMOS process is used to form npn transistors simultaneously with such gate. However, the BiCMOS process requires a large number of masks, and results in high cost. In view of this problem, as shown in FIG. 12, when nMOS transistors are used in place of npn transistors, the power transistors can be formed using the same process (CMOS process) as that of the logic circuit, thus allowing the manufacture of a recording head with relatively low cost.
An ink-jet printing method (i.e., a printing method by ejecting liquid) can realize high speed printing and has negligibly small noise produced upon printing, and has received a lot of attention recently since it can attain printing without requiring any special process, i.e., a so-called fixing process to a normal paper sheet.
Among such ink-jet printing methods, the liquid-jet printing methods described in, e.g., Japanese Patent Laid-Open No. 54-51834 and DOLS No. 2843064 have features different from other liquid-jet printing methods in that they acquire a driving force for ejecting a droplet by applying heat energy to the liquid.
More specifically, the printing method disclosed in the above references is characterized in that the liquid that received the applied heat energy undergoes changes in state accompanying an abrupt increase in volume and is ejected by an effect obtained based on the changes in state from each orifice at the distal end of a recording head to form a flying droplet, and the droplet becomes attached to a printing medium to attain recording.
Especially, the liquid-jet printing method disclosed in DOLS No. 2843064 is very effectively applied to a so-called drop-on demand printing method, and can easily realize a full-line type, high-density, multi-orifice recording head. For this reason, high-speed printing of a high-resolution, high-quality image can be achieved.
The recording head that uses the above-mentioned printing method is built by a recording head substrate which comprises liquid ejection portions having orifices formed to eject a liquid, heat applying portions which communicate with the orifices to apply heat energy for ejecting a droplet to the liquid, liquid channels including the heat applying portions, and substrate of recording head including electro-thermal conversion elements (heating elements) as means for generating heat energy.
In recent years, on such substrate, not only a plurality of heating elements are formed, but also logic circuits such as a plurality of drivers for driving the individual heating elements, a shift register for temporarily storing image data having the same number of bits as the number of heating elements to parallelly transfer the image data, serially input from a recording apparatus, to the drivers, latch circuits for temporarily latching data output from the shift register, and the like can be mounted on the single substrate.
FIG. 19 is a block diagram showing the logic circuit arrangement of a conventional recording head having N heating elements (print elements).
Referring to FIG. 19, reference numeral 700 denotes a substrate; 701, heating elements; 702, power transistors; 703, an N-bit latch circuit; and 704, an N-bit shift register. Reference numeral 715 denotes a sensor for monitoring the resistances of the heating elements 701 or the temperature of the substrate 700, or a heater for keeping the substrate 700 at a desired temperature. A plurality of such sensors and heaters may be mounted, and the sensor and heater may be integrally arranged. Reference numerals 705 to 714, and 716 denote input/output pads. Of these input/output pads, reference numeral 705 denotes a clock input pad for inputting clock pulses (CLK) for operating the shift register 704; 706, an image data input pad for serially inputting image data (DATA); 707, a latch input pad for inputting a latch clock pulses (LTCLK) for controlling the latch circuit 703 to latch image data; 708, a driving signal input pad for inputting heat pulses (HEAT) for externally controlling the driving time in which the power transistors 702 are turned on to energize and drive the heating elements 701; 709, a driving power supply input pad for inputting a driving power supply voltage (3 to 8 V, normally, 5 V) for the logic circuits; 710, a GND terminal; 711, a heating element power supply input pad for inputting a power supply voltage for driving the heating elements 701; 712, a reset input pad for inputting a reset signal (RST) for initializing the latch circuit 703 and the shift register 704; and 713, a terminal for a heating element driving power supply.
Reference numerals 714-(1) to 714-(n) denote output pads for monitoring signals and input pads for control signals for driving the sensor and the temperature control heater. Furthermore, reference numerals 716-(1) to 716-(n) denote block selection input pads for inputting block selection signals (BLK1, BLK2, . . . , BLKn) for selecting a block when the N heating elements are divided into n blocks, and the n blocks are to be time-divisionally driven. Reference numeral 717 denotes AND gates for logically ANDing the outputs from the latch circuit 702, the heat signals (HEAT), and the block selection signals (BLK1, BLK2,. . . , BLKn).
The driving sequence of the recording head with the above arrangement is as follows. Note that image data (DATA) is binary data which is defined by one bit per pixel.
When a recording apparatus main body to which the recording head is attached serially outputs image data (DATA) in synchronism with clock pulses (CLK), the output data is input to the shift register 704. The input image data (DATA) is temporarily stored in the latch circuit 703, which generates ON/OFF outputs corresponding to the value ("0" or "1" ) of image data.
In this state, when the heat pulse (HEAT) and the block selection signal are input, the latch circuit 703 supplies ON outputs, and the power transistors corresponding to the heating elements selected as a block by the block selection signal are driven during the ON time of the input heat pulse (HEAT), thus supplying currents to the corresponding heating elements to execute printing.
In the logic circuit of the recording head shown in FIG. 19, the power transistors 702 comprise npn bipolar transistors, and the logic circuit is formed using a BiCMOS process. However, in some cases, using MOSFETs as the power transistors, the logic circuit may be formed using the CMOS process as the manufacturing process in lieu of the BiCMOS process. With this process, not only the number of steps in the manufacturing process can be reduced, but also the space required for element isolation can be reduced, thus achieving a size reduction of the substrate.
This will be explained in more detail below with reference to FIGS. 20A to 22D.
FIGS. 20A and 20B are logic circuit diagrams showing a power transistor for driving a single heating element when the power transistor uses bipolar transistors. FIG. 20A is an equivalent circuit diagram of a circuit using two npn bipolar transistors 702a and 702b, and FIG. 20B is a sectional view of the substrate. Referring to FIG. 20A, a logic output 721 corresponds to the output from the AND gate 717. FIG. 20B shows how to form n-type regions 723, 725, 726, and 727, and p-type regions 724, 728, and 729 on the substrate so as to construct the npn bipolar transistor. Also, in FIG. 20B, symbols B, E, and C respectively denote the base, emitter, and collector.
FIGS. 21A to 21D are respectively a circuit diagram and sectional views of a substrate when the power transistor uses a MOSFET, and the entire logic circuit is formed by the CMOS process.
FIG. 21A is an equivalent circuit diagram of a circuit used when the power transistor for driving a single heating element uses an nMOS 720, FIG. 21B is a sectional view of the substrate that makes up the circuit shown in FIG. 21A, and FIGS. 21C and 21D are sectional views of substrates that form nMOS and pMOS transistors used in logic circuits such as the latch circuit 703, the shift register 704, and the like. In FIGS. 21B to 21D, symbols S, G, and D respectively denote the source, gate, and drain; 731, 732, and 736, n-type regions; and 733 to 735, p-type regions.
When the power transistor uses a MOSFET, the entire logic circuit can be formed by a CMOS process, and the necessity of n.sup.+ -type regions 726 and 727 for the collector, n-type epitaxial layer 725, p-type element isolation region 729, and the like (FIG. 20B), which are required in the BiCMOS process in addition to CMOS circuits including the nMOS transistors (FIG. 21C) and pMOS transistors (FIG. 21D) that form the logic circuit, can be obviated.
As a MOS power transistor, an nMOS transistor is popularly used owing to its specific electron mobility, and the like. When the nMOS transistor is used in the logic circuit of the ink-jet recording head, a voltage of 20 V or higher is applied to the drain (D) of the power transistor which is not driven. In consideration of such voltage, in order to assure such breakdown voltage, it is a common practice to form an n.sup.31 -type region in the drain region (offset type MOS transistor), as shown in FIG. 21B.